Herkese merhaba,
VHDL öğrenme yolunda yavaş adımlarla ilerlerken şöyle bir problemle karşılaştım. UART haberleşmesinde gönderdiğim veriler ile göndermek istediğim veriler arasında bir fark var. Test kodunu yazdığımda timing olarak hata görmüyorum ama usb ttl ile pc den gözlem yapmak istersem problem olduğunu görüyorum.
Yazmış olduğum kod hakkında hatamın nerede olabileceği hakkında yorumlarınızı bekliyorum
TEST KODU
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity test is
end test;
architecture modul of test is
---------------------------------------------------------------------------------
--COMPONENT definition
---------------------------------------------------------------------------------
component tx
port
(clk: in std_logic;
reset: in std_logic;
data: in std_logic_vector( 7 downto 0);
flag: out std_logic;
transmit: out std_logic);
end component tx;
---------------------------------------------------------------------------------
--SIGNAL definition
---------------------------------------------------------------------------------
signal clk : std_logic:='0';
signal reset : std_logic:='0';
signal data : std_logic_vector( 7 downto 0):= (others => '0');
signal flag : std_logic:='0';
signal transmit : std_logic:='1';
---------------------------------------------------------------------------------
--time definition
---------------------------------------------------------------------------------
signal board_osc_period : time := 20 ns;
begin
---------------------------------------------------------------------------------
--COMPONENT equalization
---------------------------------------------------------------------------------
C1: tx port map (
clk => clk,
reset => reset,
data => data,
flag => flag,
transmit => transmit
);
zamanlama: process
begin
clk<='0';
wait for board_osc_period/2;
clk<='1';
wait for board_osc_period/2;
end process;
transmint: process
begin
wait for 100 us;
flag<='0';
data<="11001100";
wait for 1040 us;
flag<='1';
wait for 100 us;
end process;
end modul;
TX kodu
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_arith.all;
entity tx is
port
(
clk: in std_logic;
reset: in std_logic;
data: in std_logic_vector( 7 downto 0);
flag: out std_logic;
transmit: out std_logic);
end tx;
architecture modul of tx is
-------------------------------------------------------------------
--COUNTERS
-------------------------------------------------------------------
signal counter: integer range 0 to 5209:=0;
signal index : integer range 0 to 7:=0;
-------------------------------------------------------------------
--BUFFERS
-------------------------------------------------------------------
signal b_data : std_logic_vector( 7 downto 0):="00000000";
signal b_transmit: std_logic:='1';
signal b_flag: std_logic:='0';
-------------------------------------------------------------------
--STATE MACHINE
-------------------------------------------------------------------
type state_m is(IDLE, START, SEND, STOP1,STOP2);
signal state_new: state_m :=IDLE;
begin
transmit <= b_transmit;
flag <= b_flag;
process(clk,reset)
begin
if (reset='1') then
counter<=0;
index<=0;
b_transmit<='1';
b_flag<='0';
b_data<="00000000";
state_new<=IDLE;
elsif rising_edge(clk) then
case state_new is
--------------------------------------
when IDLE=>
if counter=5208 then--eklendi
index<=0;
counter<=0;
b_transmit<='1';
if (b_flag='0') then
b_data<=data;
b_flag<='1';
state_new<=START;
end if;
else counter<=counter+1;
end if;--eklendi
--------------------------------------
when START=>
b_transmit<='0';--yeri değisti
if counter=5208 then
counter<=0;
state_new<=SEND;
else counter<= counter+1;
end if;
--------------------------------------
when SEND=>
b_transmit<=b_data(index);--yeri değisti
if counter=5208 then
if index=7 then
index<=0;
state_new<=STOP1;
else index<= index+1;
end if;
counter<=0;
else counter<= counter+1;
end if;
--------------------------------------
when STOP1=>
b_transmit<='1';
if counter=5208 then
counter<=0;
b_flag<='0';
state_new<=STOP2;
else counter<=counter+1;
end if;
--------------------------------------
when STOP2=>
b_transmit<='1';
if counter=2604 then
state_new<=IDLE;
else counter<=counter+1;
end if;
end case;
end if;
end process;
end modul;