FPGA içindeki PLL leri kullanmak için aşağıdaki örneği denedim.
1280x800@60Hz çıkış ve Pixel clock frekansı olan 83.46Mhz elde etmek için FPGA üzerinde ki PLL brimini kullanamak.
Neden bu çözünürlüğü seçtiğime gelince 83.46Mhz gibi küsüratlı bir frekans değeri var.
(http://i.hizliresim.com/7qlYpY.jpg)
(http://i.hizliresim.com/j89BRn.jpg)
VGA_Top_Level.vhd
-- Create Date: 20.05.2017 21:14:07
-- Design Name:
-- Module Name: VGA_Top_Level - Behavioral
-- scpecialist@yahoo.com
---------------------------
-- 1280x800@60Hz için VGA
--Pixel Clock Fr: 83.46Mhz
--HOR
----1280 pixel görünür
---- 64 Front porch
---- 136 Senkron
---- 200 Back Porch
----1680 Toplam pixel
--VER
----800 Pizel Görünür
---- 1 Front Proch
---- 3 Senkron
---- 24 Back Porch
----828 Toplam Pixel
---------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity VGA_Top_Level is
Port (
Clock_100: IN STD_LOGIC; --VECTOR (1 downto 0);
VGA_HS,VGA_VS: OUT STD_LOGIC;
VGA_R,VGA_G,VGA_B: OUT STD_LOGIC_VECTOR (3 downto 0)
);
end VGA_Top_Level;
architecture MAIN of VGA_Top_Level is
signal VGACLK: std_logic;
--------------------------------------------------
component PLL83Mhz is
port (
clk_in1: in std_logic;
clk_out: out std_logic
);
end component PLL83Mhz;
--------------------------------------------------
component SYNC is
port (
CLK : IN STD_LOGIC;
HSYNC,VSYNC: OUT std_logic;
R,G,B: OUT STD_LOGIC_VECTOR (3 downto 0)
);
end component SYNC;
begin
C1: SYNC port map (VGACLK,VGA_HS,VGA_VS,VGA_R,VGA_G,VGA_B);
C2: PLL83Mhz port map(Clock_100, VGACLK);
end MAIN;
SYNC.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
Entity SYNC is
port (
CLK : IN STD_LOGIC;
HSYNC,VSYNC: OUT std_logic;
R,G,B: OUT STD_LOGIC_VECTOR (3 downto 0)
);
end SYNC;
architecture MAIN of SYNC is
signal HPOS: integer range 0 to 1680:=0;
signal VPOS: integer range 0 to 828:=0;
begin
process (CLK)
begin
if(CLK'EVENT and CLK='1')then
if(HPOS=1040 or VPOS=428) then
R<=(others=>'1');
G<=(others=>'1');
B<=(others=>'1');
else
R<=(others=>'0');
G<=(others=>'0');
B<=(others=>'0');
end if;
if (HPOS<1680) then
HPOS<=HPOS+1;
else
HPOS<=0;
if (VPOS<828) then
VPOS<=VPOS+1;
else
VPOS<=0;
end if;
end if;
if (HPOS>64 and HPOS <200) then
HSYNC <='0';
else
HSYNC <='1';
end if;
if (VPOS>1 and VPOS <4) then
VSYNC <='0';
else
VSYNC <='1';
end if;
if ((HPOS >0 and HPOS<400) or (VPOS>0 and VPOS<28))then
R<=(others=>'0');
G<=(others=>'0');
B<=(others=>'0');
end if;
end if;
end process;
end MAIN;
pinler.xcd
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_G[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_R[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {VGA_B[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports Clock_100]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_HS]
set_property IOSTANDARD LVCMOS33 [get_ports VGA_VS]
set_property PACKAGE_PIN P19 [get_ports VGA_HS]
set_property PACKAGE_PIN R19 [get_ports VGA_VS]
set_property PACKAGE_PIN W5 [get_ports Clock_100]
set_property PACKAGE_PIN H19 [get_ports {VGA_R[1]}]
set_property PACKAGE_PIN N19 [get_ports {VGA_R[3]}]
set_property PACKAGE_PIN J19 [get_ports {VGA_R[2]}]
set_property PACKAGE_PIN G19 [get_ports {VGA_R[0]}]
set_property PACKAGE_PIN J17 [get_ports {VGA_G[0]}]
set_property PACKAGE_PIN H17 [get_ports {VGA_G[1]}]
set_property PACKAGE_PIN G17 [get_ports {VGA_G[2]}]
set_property PACKAGE_PIN D17 [get_ports {VGA_G[3]}]
set_property PACKAGE_PIN N18 [get_ports {VGA_B[0]}]
set_property PACKAGE_PIN K18 [get_ports {VGA_B[1]}]
set_property PACKAGE_PIN L18 [get_ports {VGA_B[2]}]
set_property PACKAGE_PIN J18 [get_ports {VGA_B[3]}]