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18F46K22 Digital İnput Okuyamama Sorunu

Başlatan elektroacemi, 16 Şubat 2022, 16:36:01

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elektroacemi

16 Şubat 2022, 16:36:01
Merhabalar.

XC8 e çok hakim değilim. Öğrenmeye çalışırken basit bir kod yazdım. Digital giriş okumasını bir türlü yapamadım.

GIRIS olarak farklı port da denedim olmadı. Girişte donanımsal olaral Pull-UP bağlı. ISIS üzerinde deniyorum.

// PIC18F46K22 Configuration Bit Settings

// 'C' source line config statements

// CONFIG1H
#pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal oscillator block)
#pragma config PLLCFG = OFF     // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock is always enabled)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
#pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
#pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTD2   // ECCP2 B output mux bit (P2B is on RD2)
#pragma config MCLRE = INTMCLR  // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = ON         // Code Protection Block 0 (Block 0 (000800-003FFFh) code-protected)
#pragma config CP1 = ON         // Code Protection Block 1 (Block 1 (004000-007FFFh) code-protected)
#pragma config CP2 = ON         // Code Protection Block 2 (Block 2 (008000-00BFFFh) code-protected)
#pragma config CP3 = ON         // Code Protection Block 3 (Block 3 (00C000-00FFFFh) code-protected)

// CONFIG5H
#pragma config CPB = ON         // Boot Block Code Protection bit (Boot block (000000-0007FFh) code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>
#include <pic18f46k22.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>

#define _XTAL_FREQ 8000000

#define GIRIS PORTCbits.RC7
#define ROLE1 PORTBbits.RB2
#define ROLE2 PORTBbits.RB1

void main(void) {
    
    OSCCON =0x62;       /* set internal oscillator Freq = 8 MHz*/
            //76543210
    TRISA = 0b00000000;
    TRISB = 0b00000000; 
    TRISC = 0b10000000;
    TRISD = 0b00000000; 
    TRISE = 0b00000000;
    
    PORTA = 0b00000000;
    PORTB = 0b00000000; 
    PORTC = 0b00000000;
    PORTD = 0b00000000; 
    PORTE = 0b00000000;
    
    ADCON1 = 0X06; // analog pinleri Dijitale dönü?ür.
    
    while(1)
    {
       if (GIRIS==1)
       {
           ROLE1=1;
           ROLE2=0;
       }
       if (GIRIS==0)
       {
           ROLE1=0;
           ROLE2=1;
       }
    }
}

ex_machina

#1
16 Şubat 2022, 16:51:24 Son düzenlenme: 16 Şubat 2022, 16:55:53 ex_machina
Girişi PORT registerinden okuyun, çıkışları ise LAT registeri ile sürün.

Örneğin çıkşları aşağıdaki şekilde değiştirin, bir de öyle deneyin.

#define ROLE1 LATBbits.LATB2
#define ROLE2 LATBbits.LATB1

Düzeltme: registerleri yanlış yazmışım

elektroacemi

#2
16 Şubat 2022, 17:03:10
Alıntı yapılan: ex_machina - 16 Şubat 2022, 16:51:24Girişi PORT registerinden okuyun, çıkışları ise LAT registeri ile sürün.

Örneğin çıkşları aşağıdaki şekilde değiştirin, bir de öyle deneyin.

#define ROLE1 LATBbits.LATB2
#define ROLE2 LATBbits.LATB1

Düzeltme: registerleri yanlış yazmışım


Denemiştim bunu ama tekrar denedim. Sonuç değişmedi.

mehmet

#3
16 Şubat 2022, 17:12:12 Son düzenlenme: 16 Şubat 2022, 17:16:28 mehmet
Bu durum XC8 ile alakalı değil. İlgili
mcunun kitapçığına bakarsanız pinler analog
giriş olara ön tanımlı geliyor.
ADCON1 registeri bu mcuda farklı kullanımda.
Bunun yerine ANSELA, ANSELB, ANSELC, vb.
registerleri ile analog girişler kapatılır.
İlgili mcunun I/O port tanımlamaları
bölümünü inceleyiniz. (Bölüm: 10.0)

/*
 * File:   main.c
 * Author: Mehmet
 *
 * Created on 16 Şubat 2022 Çarşamba, 17:00
 */

// PIC18F46K22 Configuration Bit Settings
// 'C' source line config statements

// CONFIG1H
#pragma config FOSC = INTIO67   // Oscillator Selection bits (Internal oscillator block)
#pragma config PLLCFG = OFF     // 4X PLL Enable (Oscillator used directly)
#pragma config PRICLKEN = ON    // Primary clock enable bit (Primary clock is always enabled)
#pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRTEN = OFF     // Power-up Timer Enable bit (Power up timer disabled)
#pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
#pragma config BORV = 190       // Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

// CONFIG2H
#pragma config WDTEN = OFF      // Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
#pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config CCP2MX = PORTC1  // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
#pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
#pragma config CCP3MX = PORTB5  // P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
#pragma config HFOFST = ON      // HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
#pragma config T3CMX = PORTC0   // Timer3 Clock input mux bit (T3CKI is on RC0)
#pragma config P2BMX = PORTD2   // ECCP2 B output mux bit (P2B is on RD2)
#pragma config MCLRE = INTMCLR  // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)

// CONFIG4L
#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = ON         // Code Protection Block 0 (Block 0 (000800-003FFFh) code-protected)
#pragma config CP1 = ON         // Code Protection Block 1 (Block 1 (004000-007FFFh) code-protected)
#pragma config CP2 = ON         // Code Protection Block 2 (Block 2 (008000-00BFFFh) code-protected)
#pragma config CP3 = ON         // Code Protection Block 3 (Block 3 (00C000-00FFFFh) code-protected)

// CONFIG5H
#pragma config CPB = ON         // Boot Block Code Protection bit (Boot block (000000-0007FFh) code-protected)
#pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <stddef.h>

#define _XTAL_FREQ 8000000

#define GIRIS PORTCbits.RC7
#define ROLE1 PORTBbits.RB2
#define ROLE2 PORTBbits.RB1

void main(void)
{
    //OSCCON =0x62;       /* set internal oscillator Freq = 8 MHz*/
    OSCCONbits.IRCF = 0b110; //Bu daha anlaşılır.

    LATA = 0x00;
    LATB = 0x00;
    LATC = 0x00;
    LATD = 0x00;
    LATE = 0x00;
    
    PORTA = 0b00000000;
    PORTB = 0b00000000;
    PORTC = 0b00000000;
    PORTD = 0b00000000;
    PORTE = 0b00000000;
    
    //76543210
    TRISA = 0b00000000;
    TRISB = 0b00000000;
    TRISC = 0b10000000;//C7 giriş
    TRISD = 0b00000000;
    TRISE = 0b00000000;

    //ADCON1 = 0X06; // analog pinleri Dijitale dönü?ür.
    ANSELA = 0x00;
    ANSELB = 0x00;
    ANSELC = 0x00;
    ANSELD = 0x00;
    ANSELE = 0x00;    

    while(1)
    {
        if(GIRIS == 0b1)
        {
            __delay_ms(50);
            if(GIRIS == 0b1)
            {
                ROLE1 = 1;
                ROLE2 = 0;
            }
        }
        else if(GIRIS == 0b0)
        {
            ROLE1 = 0;
            ROLE2 = 1;
        }
    }
}
////////////////////////////////////////////////////////////////////////////////


Olan olmuştur,
olacak olan da olmuştur.
Olacak bir şey yoktur.
---------------------------------------------
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#4
16 Şubat 2022, 19:05:09
Kütüpane dosyalarını Sayfanın en üstüne ekleyip deneyebilirsiniz.
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