Pic18f4550 PLL Config

[kenan_re]

Bu şekilde bir ayar yaptığımda iç frekans ne kadar oluyor. Bir türlü kafama yatmadı bu olay.
20 MHZ kristalim var. Seri Port haberleşmesi ve kesme fonsiyonu bu sigortalarla çalışmıyor.

// CONFIG1L
        #pragma config PLLDIV = 1       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))

        #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])

        #pragma config USBDIV = 1       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)


        // CONFIG1H
        #pragma config FOSC = HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))

        #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)

        #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)


        // CONFIG2L
        #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)

        #pragma config BOR = OFF        // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)

        #pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)

        #pragma config VREGEN = OFF     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)


        // CONFIG2H
        #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))

        #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)


        // CONFIG3H
        #pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)

        #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)

        #pragma config LPT1OSC = OFF    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)

        #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)


        // CONFIG4L
        #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)

        #pragma config LVP = OFF         //RB5     Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)

        #pragma config ICPRT = OFF      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)

        #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))


        // CONFIG5L
        #pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)

        #pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)

        #pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)

        #pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)


        // CONFIG5H
        #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)

        #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)


        // CONFIG6L
        #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)

        #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)

        #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)

        #pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)


        // CONFIG6H
        #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)

        #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)

        #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)


        // CONFIG7L
        #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)

        #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)

        #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)

        #pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)


        // CONFIG7H
        #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

[kenan_re]

Çözülmüştür arkadaşlar örneğinide buraya bırakayım.

Pic18f4550 20Mhz işlemci PLL ile 48 Mhz Usart haberleşmesi.
fuse.h

   // CONFIG1H
      #pragma config FOSC = HSPLL_HS  // Oscillator Selection bits (HS oscillator, PLL enabled (HSPLL))

      #pragma config FCMEN = ON      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)

      #pragma config IESO = ON       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

   // CONFIG2L
      #pragma config PWRT = OFF       // Power-up Timer Enable bit (PWRT disabled)

      #pragma config BOR = OFF        // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)

      #pragma config BORV = 3         // Brown-out Reset Voltage bits (Minimum setting)

      #pragma config VREGEN = ON     // USB Voltage Regulator Enable bit (USB voltage regulator disabled)


   // CONFIG2H
      #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))

      #pragma config WDTPS = 128    // Watchdog Timer Postscale Select bits (1:32768)


   // CONFIG3H
      #pragma config CCP2MX = ON      // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)

      #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)

      #pragma config LPT1OSC = ON    // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for higher power operation)

      #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)


// CONFIG1L
      #pragma config PLLDIV = 5       // PLL Prescaler Selection bits (No prescale (4 MHz oscillator input drives PLL directly))

      #pragma config CPUDIV = OSC1_PLL2// System Clock Postscaler Selection bits ([Primary Oscillator Src: /1][96 MHz PLL Src: /2])

      #pragma config USBDIV = 2       // USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) (USB clock source comes directly from the primary oscillator block with no postscale)


   // CONFIG4L
      #pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)

      #pragma config LVP = OFF         //RB5     Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)

      #pragma config ICPRT = ON      // Dedicated In-Circuit Debug/Programming Port (ICPORT) Enable bit (ICPORT disabled)

      #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
      // CONFIG5L
      #pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) is not code-protected)

      #pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) is not code-protected)

      #pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) is not code-protected)

      #pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) is not code-protected)


      // CONFIG5H
      #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) is not code-protected)

      #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM is not code-protected)


      // CONFIG6L
      #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) is not write-protected)

      #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) is not write-protected)

      #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) is not write-protected)

      #pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) is not write-protected)


      // CONFIG6H
      #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) are not write-protected)

      #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) is not write-protected)

      #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM is not write-protected)

   // CONFIG7L
      #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks)

      #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks)

      #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks)

      #pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) is not protected from table reads executed in other blocks)


      // CONFIG7H
      #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) is not protected from table reads executed in other blocks)

main.c

#include <pic18.h>
#include <usart.h>
#include <delays.h>

#include "fuse.h"
#define _XTAL_FREQ 48000000L
        
void main()
{
	TRISA=0x00;	TRISB=0x00; TRISC=0b01000000; TRISD=0x00; TRISE=0x00;
	
	PORTA=0; PORTB=0; PORTC=0; PORTD=0; PORTE=0;
	
CCP1CON=0x00;CCP2CON=0x00;

baudUSART (
				BAUD_IDLE_RX_PIN_STATE_HIGH & 
				BAUD_IDLE_TX_PIN_STATE_HIGH &
				BAUD_IDLE_CLK_LOW &
                BAUD_16_BIT_RATE &
                BAUD_WAKEUP_OFF &
                BAUD_AUTO_OFF); 
	
// configure USART
OpenUSART((USART_ADDEN_OFF & 
USART_TX_INT_OFF
&USART_RX_INT_ON
&USART_ASYNCH_MODE
&USART_EIGHT_BIT
&USART_CONT_RX
&USART_BRGH_HIGH), 1249);
 
//USART Kesme ayarları
RCIF	=0x00;		// usart alma kesmesi açık(PIR,5 biti)
TXIE	=0x00;		// usart gönderme kesmesi kapalı(Pie1,4 biti)
RCIE	=0x01;		// usart alma kesmesi açık(Pie1,5 biti))----Gönder/Alma esnasında açıp kapatıyorum

PEIE	= 0x01; 	// Yardımcı kesme izni veriliyor(INTCON,6. biti)
GIE		= 0x01; 	// Genel kesme izni veriliyor(INTCON,7. biti)

while(1)
	{
	PORTB=0x00;
	Delay10KTCYx(150);
	
	PORTB=0xff;
	Delay10KTCYx(150);

	}
}

static void interrupt // Kesme fonksiyonu
kesme(void) 			  // Kesme fonksiyon ismi (önemsiz)
{
if(DataRdyUSART())
     {
		PORTD =	ReadUSART();
		WriteUSART(PORTD);
     }
	
}