power on reset gerçekleşmez ise;

[ido2323]

Hayırlı akşamlar RB4 ve RB3 pinlerini analog giriş yapmaya çalışıyoruz bunun için PBADEN kayıtçısı Config3H 'da ON yapılır ve bu sayede power on resette RB<5-0> analog giriş olur ve ANSELB'ye  b'00011111' değeri yüklenince de analog olur, fakat aşşağıdaki gibi yapınca çalışması gereken program çalışmıyor o halde
power on reset hangi durumlar da neden meydana gelmez? Teşekkürler

#include "p18F46K22.inc"

; CONFIG1H
  CONFIG  FOSC = INTIO67           ; Oscillator Selection bits (HS oscillator (medium power 4-16 MHz))
  CONFIG  PLLCFG = OFF          ; 4X PLL Enable (Oscillator used directly)
  CONFIG  PRICLKEN = ON         ; Primary clock enable bit (Primary clock is always enabled)
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
  CONFIG  IESO = OFF            ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

; CONFIG2L
  CONFIG  PWRTEN = OFF          ; Power-up Timer Enable bit (Power up timer disabled)
  CONFIG  BOREN = SBORDIS       ; Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
  CONFIG  BORV = 190            ; Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)

; CONFIG2H
  CONFIG  WDTEN = OFF            ; Watchdog Timer Enable bits (WDT is always enabled. SWDTEN bit has no effect)
  CONFIG  WDTPS = 32768         ; Watchdog Timer Postscale Select bits (1:32768)

; CONFIG3H
  CONFIG  CCP2MX = PORTC1       ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
  CONFIG  PBADEN = ON           ; PORTB A/D enable bit (PORTB<5:0> pins are configured as analog input channels on Reset)
  CONFIG  CCP3MX = PORTE0       ; P3A/CCP3 Mux bit (P3A/CCP3 input/output is not multiplexed with RB5)
  CONFIG  HFOFST = ON           ; HFINTOSC Fast Start-up (HFINTOSC output and ready status are not delayed by the oscillator stable status)
  CONFIG  T3CMX = PORTC0        ; Timer3 Clock input mux bit (T3CKI is on RC0)
  CONFIG  P2BMX = PORTD2        ; ECCP2 B output mux bit (P2B is on RD2)
  CONFIG  MCLRE = EXTMCLR       ; MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)

; CONFIG4L
  CONFIG  STVREN = ON           ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
  CONFIG  LVP = ON              ; Single-Supply ICSP Enable bit (Single-Supply ICSP enabled if MCLRE is also 1)
  CONFIG  XINST = OFF           ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

; CONFIG5L
  CONFIG  CP0 = OFF             ; Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
  CONFIG  CP1 = OFF             ; Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
  CONFIG  CP2 = OFF             ; Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
  CONFIG  CP3 = OFF             ; Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)

; CONFIG5H
  CONFIG  CPB = OFF             ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
  CONFIG  CPD = OFF             ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)

; CONFIG6L
  CONFIG  WRT0 = OFF            ; Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
  CONFIG  WRT1 = OFF            ; Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
  CONFIG  WRT2 = OFF            ; Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
  CONFIG  WRT3 = OFF            ; Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)

; CONFIG6H
  CONFIG  WRTC = OFF            ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
  CONFIG  WRTB = OFF            ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
  CONFIG  WRTD = OFF            ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)

; CONFIG7L
  CONFIG  EBTR0 = OFF           ; Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
  CONFIG  EBTR1 = OFF           ; Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
  CONFIG  EBTR2 = OFF           ; Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
  CONFIG  EBTR3 = OFF           ; Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)

; CONFIG7H
  CONFIG  EBTRB = OFF           ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)



;,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
    #define LCD_D7   LATD,0      ;
    #define LCD_D6   LATD,6      ;
    #define LCD_D5   LATD,2      ;
    #define LCD_D4   LATD,3      ;
    #define LCD_RS   LATD,5      ;
    #define LCD_E    LATD,4      ;
    #define PORTBB   PORTB,0      ;
;============================================================


	        ORG     0X0000            ; ba?lang?ç vektörü

  		goto    main              ; ana programa ;dallan

ORG     0X0020
main
;port tan?mlamalar? yap?l?yor.

movlw b'01100110'
movwf OSCCON

;movlw b'11110000'
;movwf VREFCON0

;MOVLW b'10010000' ; Turn off
;MOVWF CM2CON1 ; comparator

AN00 MACRO
MOVLW b'00000000' ;
MOVWF ADCON0 ; for digital inputs
ENDM
AN01 MACRO
MOVLW b'00000100' ; Configure A/D
MOVWF ADCON0 ; for digital inputs
ENDM
AN02 MACRO
MOVLW b'00001000' ; Configure A/D
MOVWF ADCON0 ; for digital inputs
ENDM
AN03 MACRO
MOVLW b'00110100' ; Configure A/D
MOVWF ADCON0 ; for digital inputs
ENDM
AN04 MACRO
MOVLW b'00101100' ; Configure A/D
MOVWF ADCON0 ; for digital inputs
ENDM
AN05 MACRO
MOVLW b'00100100' ; Configure A/D
MOVWF ADCON0 ; for digital inputs
ENDM
MOVLW b'10111111' ; Configure A/D
MOVWF ADCON2 ; for digital inputs
MOVLW b'10000100'
MOVWF ADCON1 

movlw b'00011111'
movwf ANSELB


CLRF LATD
MOVLW 0X00
MOVWF TRISD
CLRF PORTB
CLRF LATB
MOVLW 0XFF
MOVWF TRISB
CLRF PORTA
MOVLW 0XFF
MOVWF TRISA

[FEHMİ_ASM]

   Arkadaşım elindeki pic in konfigürasyonunu bilmiyorum, ilgisi var mı şüpheye düştüm. Power on reset ve power timer'i ile yaptığın analog işlemin ne ilgisi var anlayamadım. Sanki bir kavram karmaşası var. Lütfen linkteki yazıyı oku.

https://www.picproje.org/index.php?topic=33541.0

[ido2323]

power timer ile bir sıkıntım yok o nereden çıktı anlamadım Bknz; sayfa 298(note 3.), sayfa 360
http://ww1.microchip.com/downloads/en/DeviceDoc/41412F.pdf

bu arada sayfa 140;

"Note: On a Power-on Reset, RB<5:0> are
configured as analog inputs by default and
read as '0'; RB<7:6> are configured as
digital inputs.
When the PBADEN Configuration bit is
set to '1', RB<5:0> will alternatively be
configured as digital inputs on POR."
mesaj birleştirme:: 23 Mart 2015, 21:21:25
Konu kilit kod doğru pic bozuk ilk kez B portları bozuk bir pic denk geldi başkasını takınca düzeldi.